Method for the formation of polycide gate in semiconductor device

ABSTRACT

A method for the formation of gate in a semiconductor device is disclosed. The method for the formation of gate in a semiconductor device, comprising the steps of: forming amorphous silicon and polysilicon over a gate insulating film atop a semiconductor substrate, in due order; implanting impurity ions into the polysilicon and carrying out heat treatment; and forming a layer of a refractory metal over the silicon and carrying out heat treatment, to form polycide. Capable of preventing the degradation which is attributed to the penetration of impurities and thermal instability when forming a P +   polygate, the method contribute to the improvement in electrical properties.

This application is a continuation of application Ser. No. 08/251,703,filed May 31, 1994, now abandoned.

BACKGROUND OF THE INVENTION

The present invention relates, in general, to a method for fabrication asemiconductor device and, more particularly, to a method for forming agate, capable of improving electrical properties.

In conventional methods for forming a gate of a hyperfine P-MOSFET, highdensity P type (P⁺) polysilicon doped with B⁺ or BF₂ ⁺ is utilized, inorder to prevent short channel effect.

The implantation of BF₂ ⁺, which has been most widely carried out toform a shallow junction when P type junction is built, has an advantageof simplifying the formation processes for gate when it is utilized todope polysilicon. However, the formation of gate by depositing a gateinsulating film over a silicon substrate, depositing polysilicon dopedwith BF₂ ⁺ and selectively etching the polysilicon cause the fluorine ofBF²⁺ to accelerate the penetration of boron into the silicon substrateand hence degrades the electrical properties of channel region.

In a gate formation method utilizing polycide, the polysilicon filmsover a source and drain region and a gate region can be formed intoself-align silicide (hereinafter referred to as "salicide"),simultaneously at a step of forming silicide, and hence the processescan be simplified.

However, since this method utilizes a refractory metal, such as Ti andCo, in order to form the silicide of TiSi₂ or CoSi₂, there are someproblems.

For example, in case of forming the silicide of TiSi₂, as reported in"Silicide-Silicon interface degradation during Ti/polysilicon oxidation"to M. Tanielian, R Lajos, and S. Blackstone, Electrochem. Soc., 132,1456 (1985), the thickness of the silicide becomes nonuniform due to thefact that the silicon is nonuniformly exhausted (nonuniformsilicide-silicon interface) when forming the silicide. In case of thelatter, as disclosed in "Stability of polycrystalline Silicon-on-CobaltSilicide-Silicon Structure" to S. P. Murada, C. C. Chang, A. C. Adams,J. Vac. Sci. Technol., B(5), 865(1987), since the lattice parameter ofCo is similar to that of silicon, the phenomenon of recrystallizationand grain growth reverse the order of a layer of silcide and a layer ofpolysilicon.

Accordingly, there is desperately required a novel method for theformation of gate in a semiconductor device, in order to solve theproblems.

In order to better understand the background of the present invention,conventional methods for forming a gate in a semiconductor device are tobe described with reference to figures.

Referring initially to FIGS. 1A through 1D, there is illustrated aconventional formation method for gate.

First, as illustrated in FIG. 1A, over a silicon substrate 1 is formed agate insulating film 2 formed, on which a polysilicon 4 is thendeposited.

Next, as illustrated in FIG. 1B, BF₂ ⁺ ions are implanted entirely intothe polysilicon 4 as indicated by arrows, and an annealing process iscarried out to allow the polysilicon to have a columnar structure.

Thereafter, as illustrated in FIG. 1C, over the polysilicon 4, there isdeposited Co 5, a refractory metal.

Finally, as illustrated in FIG. 1d, the result is annealed at about 900°C., to yield CoSi₂, and a selective etch process is carried out, to forma gate of semiconductor device.

Referring now to FIGS. 2A through 2D, there is illustrated anotherconventional formation method for gate.

First, as illustrated in FIG. 2A, over a silicon 11 is a gate insulatingfilm 12 formed on which amorphous silicon 3 is then deposited.

Next as illustrated in FIG. 2B BF₃ ⁺ ions are implanted entirely intothe amorphous silicon 13 as indicated by arrows, and an annealingprocess is carried out to allow the amorphous silicon to have arecrystallization structure. As a result, the structure of thisamorphous silicon is larger than that of the polysilicon employed in thepreviously mentioned method.

Thereafter, as illustrated in FIG. 1C, over the polysilicon 13, there isdeposited Co 15, a refractory metal.

Finally, as illustrated in FIG. 1D, the resulting is annealed at about900° C., to yield CoSi₂, and a selective etch process is carried out, toform a gate of semiconductor device.

Such conventional methods as are described above are problematic in thefollowing aspects.

First, the columnar structure of the polysilicon causes the pipe-linediffusion of dopant along a grain boundary which is vertically formed ondoping with the dopants.

Next, the recrystallization structure of the amorphous silicon alsocauses the penetration of dopant like the columnar structure.

In addition, after completing either of the conventional methods, theinterface between CoSi₂ and Si is non-uniformly formed.

SUMMARY OF THE INVENTION

Therefore, an object of the present invention is to overcome the aboveproblems encountered in prior arts and to provide a method for forming agate in a semiconductor device, capable of restraining the penetrationof impurities and providing thermal stability.

In accordance with the present invention, the above object of thepresent invention can be accomplished by providing a method for theformation of gate in a semiconductor device, comprising the steps of:forming amorphous silicon and polysilicon over a gate insulating filmatop a semiconductor substrate, in due order; implanting impurity ionsinto the polysilicon and carrying out heat treatment; and forming alayer of a refractory metal over the silicon and carrying out heattreatment, to form polycide.

BRIEF DESCRIPTION OF THE DRAWINGS

The above object and other advantages of the present invention willbecome more apparent by describing in detail the preferred embodiment ofthe present invention with reference to the attached drawings in which:

FIGS. 1A through 1D are schematic, cross sectional views illustrating aconventional method for forming a Gate in a semiconductor device;

FIGS. 2A through 2D are schematic, cross sectional views illustratinganother conventional method for forming a gate in a semiconductordevice;

FIGS. 3A through 3D are schematic, cross sectional views illustrating amethod for the formation of gate in a semiconductor device, according tothe present invention;

FIG. 4 is a graph showing the changes of face resistance with regard tothe heat treatment time;

FIG. 5 is a graph showing relation of the I-V characteristics ofsilicides;

FIGS. 6A through 6D are graphs showing the C-V characteristics ofsilicides.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

Hereinafter, the preferred embodiments of the present invention will bedescribed with reference to the accompanying drawings.

Referring initially to FIG. 3, there is illustrated a method for theformation of gate in a semiconductor device, according to the presentinvention.

First, as illustrated in FIG. 3A, over a silicon substrate 1, there isdeposited N₂ O, so as to form a gate insulating film which is 80 Åthick. It is also illustrated in this figure that amorphous silicon is 3deposited on the gate insulating film, followed by the deposition ofpolysilicon on the amorphous silicon 3.

Subsequently, as illustrated in FIG. 3B, BF₂ ⁺ ions are entirelyimplanted into the polysilicon, and an annealing process is carried outto form a horizontal grain boundary H between the amorphous silicon andthe polysilicon, wherein the vertical grain boundaries formed in theamorphous silicon and the polysilicon are not connected with each otherdue. As a result of the disconnection, no penetration of dopants occurs.At the moment, the polysilicon 4 must have a thickness in which it isexpected to be consumed when polycide is formed later.

Thereafter, as illustrated in FIG. 3C, over the polysilicon 4 is Co 5, arefractory metal, deposited.

Finally, as illustrated in FIG. 3D, the resulting structure is subjectedto heat processing. At this time, the polysilicon 4 and the Co 5 react,to form a uniform thickness of polycide 6, CoSi₂. A gate ofsemiconductor device can be completed by selectively etching thepolycide 6 formed and the amorphous silicon 3.

This method according to the present invention takes advantages over theconventional methods, as follow.

First, since the BF₂ ⁺ ion-implantation and subsequent annealing iscarried out in back of the deposition of amorphous silicon andpolysilicon over the silicon substrate, the gate of the presentinvention is much superior to the conventional ones in face resistance,that is, conductivity.

Second, the measurement of I-V characteristics after the formation ofgate reveals that there are larger break down voltage and less leakcurrent.

Third, the measurement of C-V characteristics after the formation ofgate reveals that there is a better effect in electrical properties.

With regard to these effects, more detailed description will be given byreferring to some drawings.

FIG. 4 shows the changes of face resistances according to thermalprocessing times in a variety of silicon films.

To begin with, the total thickness of the silicon thin film for gate isset 3,500 Å. Legend 1 denotes a first silicon thin film consisting ofamorphous silicon and polysilicon which are deposited in a thickness of2,500 and 1,000 Å, respectively. This is the case of the presentinvention. Legend 2 denotes a second silicon thin film consisting ofonly amorphous silicon which is deposited in a thickness of 3,500 Å.Legend 3 designates a third silicon thin film consisting of firstpolysilicon and second polysilicon which are deposited in a thickness of2,500 and 1,000 Å, respectively, whereas the legend 4 indicates a fourthsilicon thin film consisting of only polysilicon which is deposited in athickness of 3,500 Å. Into these four silicon thin films, BF₂ ⁺ ions areimplanted at a dose of 4×10¹⁵ cm⁻² ions/cm² and at an accelerationenergy of 35 Kev. Thereafter, the silicon thin films are treated at 900°C. for 70 minutes.

Face resistance values are plotted with regard to the heat treatmenttime of 6 to 70 minutes and compared. As shown in FIG. 4, the firstsilicon thin film is superior to the other silicon thin films in faceresistance, that is, conductivity.

Referring now to FIG. 5, there are shown the I-V characteristics of avariety of CoSi₂ including the present invention.

To begin with, the total thickness of the silicon thin film for gate isset 3,500 Å. Legend 1 denotes first CoSi₂ which is formed by depositingamorphous silicon and polysilicon over a gate insulating film in athickness of 2,500 and 1,000 Å, respectively, implanting BF₂ ^(+into)the silicon thin film, treating with heat, depositing Co and carryingout another heat treatment. Legend 2 designates second CoSi₂ which isformed in a manner similar to that of the first CoSi₂ except that onlyamorphous silicon is deposited in a thickness of 3,500 Å instead of theamorphous silicon and polysilicon. Legend 3 indicates third CoSi₂ whichis formed in a manner similar to that of the first CoSi₂ except thatfirst polysilicon and second polysilicon are deposited in a thickness of2,500 and 1,000 Å, respectively instead of the amorphous silicon andpolysilicon, whereas legend 4 does fourth CoSi₂ formed in a mannersimilar to that of the first CoSi₂ except that only polysilicon isdeposited in a thickness of 3,500 Å instead of the amorphous silicon andpolysilicon.

The I-V characteristics of the four CoSi₂ are compared, showing that thefirst CoSi₂ has larger break down voltage and less leak current than theother CoSi₂.

Turning now into FIG. 6A through 6D, there are shown the C-Vcharacteristics of a variety of CoSi₂ including the present invention.

To begin with, the total thickness of the silicon thin film for gate isset 3,500 Å. Legend 1 denotes first CoSi₂ which is formed by depositingamorphous silicon and polysilicon over a gate insulating film in athickness of 2,500 and 1,000 Å, respectively, implanting BF₂ ^(+into)the silicon thin film, treating with heat, depositing Co and carryingout another heat treatment. Legend 2 designates second CoSi₂ which isformed in a manner similar to that of the first CoSi₂ except that onlyamorphous silicon is deposited in a thickness of 3,500 Å instead of theamorphous silicon and polysilicon. Legend 3 indicates third CoSi₂ whichis formed in a manner similar to that of the first CoSi₂ except thatfirst polysilicon and second polysilicon are deposited in a thickness of2,500 and 1,000 Å, respectively instead of the amorphous silicon andpolysilicon, whereas legend 4 does fourth CoSi₂ formed in a mannersimilar to that of the first CoSi₂ except that only polysilicon isdeposited in a thickness of 3,500 Å instead of the amorphous silicon andpolysilicon.

The C-V characteristics of the four CoSi₂ are compared, showing that thefirst CoSi₂ is superior to the other CoSi₂ in electrical properties.

As described hereinbefore, the method according to the present inventionis capable of preventing the degradation which is attributed to thepenetration of impurities and thermal instability when forming a P⁺polygate. Accordingly, it can contribute to the improvement inelectrical properties.

Other features, advantages and embodiments of the invention disclosedherein will be readily apparent to those exercising ordinary skill afterreading the foregoing disclosures. In this regard, while specificembodiments of the invention have been described in considerable detail,variations and modifications of these embodiments can be effectedwithout departing from the spirit and scope of the invention asdescribed and claimed.

What is claimed is:
 1. A method for fabricating a semiconductor device,comprising the steps of:(a) providing a semiconductor substrate having agate insulating film thereon; (b) forming an amorphous silicon layerabout 2,500 angstroms thick on the gate insulating film; (c) forming apolysilicon layer on the amorphous silicon layer, the polysilicon layerbeing thinner than the amorphous silicon layer; (d) implanting impurityions into the polysilicon layer such that a concentration of theimpurity ions in the polysilicon layer is higher than a concentration ofthe impurity ions in the amorphous silicon layer, wherein the impurityions are BF₂ ions; (e) after step (d), conducting heat treatment on thesemiconductor device, thereby forming vertical grain boundaries in theamorphous silicon layer and forming vertical grain boundaries in thepolysilicon layer, wherein the vertical grain boundaries formed in theamorphous silicon layer are not connected with the vertical grainboundaries formed in the polysilicon layer; and then (f) forming arefractory metal layer on the polysilicon layer and then annealing therefractory metal layer to form a polycide.
 2. The method of claim 1,wherein said annealing step forms the polycide on silicon of a gateelectrode and the polycide reduces the resistance of the gate electrode.3. The method of claim 1, wherein the polysilicon layer has a thicknesssuch that the polysilicon layer is consumed when the polycide is formedduring said annealing step.
 4. The method of claim 1, wherein the metalof the refractory metal layer is cobalt.
 5. The method of claim 1,wherein step (e) causes the implanted impurity ions to diffuse into theamorphous silicon layer and the polysilicon layer.
 6. The method ofclaim 1, wherein the heat treatment of step (e) is done at about 900degrees Celsius for about 70 minutes.
 7. The method of claim 1, whereinthe polysilicon layer is about 1,000 angstroms thick.
 8. The method ofclaim 1, wherein the gate insulating film is about 80 angstroms thick.